Design of Resource Efficient FIR Filter Structure Using Adders and Multiplier
نویسندگان
چکیده
This paper presents high speed digital Finite Impulse Response (FIR) filter relying on Wallace tree multiplier and Carry Select Adder (CSLA). Adder has three architectures such as basic CSLA using RCA (Ripple Carry Adder), CSLA using BEC (Binary to Excess-1 Converter) and CSLA using D-latch. In this paper we propose 4tap FIR Filter architecture using 16-bit CSLA using D-latch and 8-bit Wallace tree multiplier. These multipliers and adders are used for high speed operation of digital FIR filter.
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